View NJW1184_7259685.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJW1184 -1- 4-channel electronic volume general description package outline the NJW1184 is a four channel electronic volume. the NJW1184 performs click-noiseless characteristics with vca circuit. these functions are controlled by i2c bus. and the slave address selector is available for using two chips on same serial bus line. it?s available for two-channel stereo and or multi-channel audio volume. features operating voltage 7.5 to 13v i 2 c bus control slave address selector available for using two chips on same serial bus line volume (vca type) 0 to ?100db/0.5dbstep, mute 2 auxiliary port bi-cmos technology package outline dmp20, dip20 block diagram bias vol3 out3 out4 cvol1 cvol2 cvol3 cvol4 gnd v+ vref scl sda vol4 aux0 in4 in3 adr aux1 i 2 c bus interface vol1 out1 out2 vol2 in2 in1 NJW1184m NJW1184d
NJW1184 - 2 - pin configuration no. symbol function no symbol function 1 in1 input 1 11 v+ power supply pin 2 out1 output 1 12 vref reference voltage 3 in2 input 2 13 aux0 auxiliary output0 4 out2 output 2 14 aux1 auxiliary output1 5 cvol1 dac output for volume 1 15 cvol4 dac output for volume 4 6 cvol2 dac output for volume 2 16 cvol3 dac output for volume 3 7 adr slave address setting 17 out4 output 4 8 sda sda data input (i 2 c bus) 18 in4 input 4 9 scl scl data input (i 2 c bus) 19 out3 output 3 10 gnd gnd 20 in3 input 3 2 3 4 5 6 7 8 9 10 1 20 19 18 17 16 in1 out1 in2 cvol2 a dr out2 cvol1 sd a scl gnd in3 out3 in4 cvol4 a ux1 cvol3 a ux0 vref v+ 15 14 13 12 11 out4
NJW1184 -3- absolute maximum rating (ta=25c) parameter symbol rating unit supply voltage v + 15 v maximum input voltage v im 0 to v + ( ? ) v power dissipation p d dip20 : 700 dmp20 : 350 mw operating temperature range topr -40 to +85 c storage temperature range tstg -40 to +125 c ( ? ) for the maximum input voltage less than 0 tov + electrical characteristics (ta=25c, v+=9v, r l =47k ? , vin=100mvrms/1khz, unless otherwise specified) power supply parameter symbol test condition min. typ. max. unit operating voltage v + 7.5 9.0 13.0 v supply current i cc no signal - 4 10 ma reference voltage v ref no signal 4.0 4.5 5.0 v volume parameter symbol test condition min. typ. max. unit maximum input voltage v im vol=-20db,thd=1% 2.8 3.0 - vrms maximum output voltage v om output vol=0db,thd=1% - 2.5 - vrms channel balance g cb vol=0db -1.0 0.0 1.0 db total harmonic distortion thd vo=0.5vrms bw=400hz to 30khz - - 0.3 % maximum gain g vmax vol= 0db -2.0 0.0 2.0 db minimum gain g vmin vol= mute, vin=2vrms - -100 -90 db channel separation cs vin = 1vrms a-weighting - -80 -70 db output noise 1 v no1 vol = 0db a-weighting - - -90 (31.6) -85 (56.2) dbv ( vrms) output noise 2 v no2 vol = mute a-weighting - - -106 (5.0) -96 (15.8) dbv ( vrms) input impedance ri - 20 - k ? logic output: high 4.5 - 5.5 aux output voltage v aux logic output: low 0 - 0.5 v bw: band width control parameter symbol test condition min. typ. max. unit high level input voltage v adrh high : slave address 82h v + /2 - - v low level input voltage v adrl low : slave address 80h - - 1.0 v
NJW1184 - 4 - i 2 c bus characteristics (sda, scl) i 2 c bus load conditions: pull up resistance 4k ? (connected to +5v), load capacitance 200pf (connected to gnd) standard mode fast mode parameter symbol min. typ. max. min. typ. max. unit low level input voltage v il 0.0 - 1.5 0.0 - 1.5 v high level input voltage v ih 2.7 - 5.0 2.7 - 5.0 v hysteresis of schmitt trigger inputs v hys - - - 0.25 - - v low level output voltage (3ma at sda pin) v ol 0 - 0.4 0 - 0.4 v output fall time from v ihmin to v ilmax with a bus capacitance from 10pf to 400pf t of - - 250 20 +0.1c b - 250 ns pulse width of spikes which must be suppressed by the input filter t sp - - - 0 - 50 ns input current each i/o pin with an input voltage between 0.1v dd and 0.9v ddmax i i -10 - 10 -10 - 10 a capacitance for each i/o pin c i - - 10 - - 10 pf scl clock frequency f scl - - 100 - - 400 khz hold time (repeated) start condition. t hd:sta 4.0 - - 0.6 - - s low period of the scl clock t low 4.7 - - 1.3 - - s high period of the scl clock t high 4.0 - - 0.6 - - s set-up time for a repeated start condition t su:sta 4.7 - - 0.6 - - s data hold time t hd:dat 0 - 3.45 0 - 0.9 s data set-up time t su:dat 250 - - 100 - - ns rise time of both sda and scl signals t r - - 1000 - - 300 ns fall time of both sda and scl signals t f - - 300 - - 300 ns set-up time for stop condition t su:sto 4.0 - - 0.6 - - s bus free time between a stop and start condition t buf 4.7 - - 1.3 - - s capacitive load for each bus line c b - - 400 - - 400 pf noise margin at the low level v nl 0.5 - - 0.5 - - v noise margin at the high level v nh 1 - - 1 - - v c b ; total capacitance of one bus line in pf. sda scl t f t hd:sta t low t r t hd:dat t high t f t su:dat s s s s t su:sta t hd:sta t sp t su:sto s s s sr r r r t r t buf p p p p s s s s
NJW1184 -5- 50 ? fb v + ! ! ! ! terminal description pin no. symbol function equivalent circuit terminal dc voltage 1 3 20 18 in1 in2 in3 in4 input 1 input 2 input 3 input 4 v + /2 2 4 19 17 out1 out2 out3 out4 output 1 output 2 output 3 output 4 v + /2 5 6 16 15 cvol1 cvol2 cvol3 cvol4 dac output for volume 1 dac output for volume 2 dac output for volume 3 dac output for volume 4 v + /2 ? 0.7v (0db setting) 7 adr slave address setting 82(h) v adr > v + /2 80(h) v adr < 1.0v 20k ? v + 8k ? v + 12k ? 4k ? v +
NJW1184 - 6 - ! ! ! ! terminal description pin no. symbol function equivalent circuit terminal dc voltage 8 9 sda scl sda data input (i 2 c bus) scl data input (i 2 c bus) - 12 vref reference voltage v + /2 13 14 aux0 aux1 auxiliary output 0 auxiliary output 1 0v / 5v 12k ? 4k ? scl:gnd sda:ack vreg 5v 200k ? v + 50 ? vreg 5v v + v +
NJW1184 -7- application circuit 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 in1 NJW1184 out1 out2 in2 cvol1 cvol2 sda a d r in3 out3 out4 in4 cvol3 cvol4 aux0 aux1 scl gnd vre f v+ 10 f 1 f 1 f 1 f 1 f 1 f 0.47 f 0.47 f0.47 f 0.47 f 4.7 f 4.7 f 4.7 f 4.7 f + + + + + + + + + +
NJW1184 - 8 - definition of i 2 c register i 2 c bus format msb lsb msb lsb msb lsb s slave address a select address a data a p 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit s: starting term a: acknowledge bit p: ending term slave address msb lsb 1 0 0 0 0 0 adr r/w adr: hardware pin programmable address bits 80(h), 82(h) r/w=0: write mode for register setting r/w=1: not available control register table the select address sets each function (volume, aux). the auto-increment function cycles the select address as follows. 00h 01h 02h 03h 04h 00h bit select address d7 d6 d5 d4 d3 d2 d1 d0 00h vol-1 01h vol-2 02h vol-3 03h vol-4 04h don?t care don?t care don?t care don?t care don?t care don?t care aux1 aux0 control register default value control register default value is all ?0?. bit select address d7 d6 d5 d4 d3 d2 d1 d0 00h 0 0 0 0 0 0 0 0 01h 0 0 0 0 0 0 0 0 02h 0 0 0 0 0 0 0 0 03h 0 0 0 0 0 0 0 0 04h 0 0 0 0 0 0 0 0
NJW1184 -9- i 2 c control command description a) master volume (select address: 00h, 01h, 02h, 03h) volume level : 0 to ?100db(0.5db/step), mute vol-1 / vol-2 / vol-3 / vol-4 gain(db) hex d7 d6 d5 d4 d3 d2 d1 d0 0 ff 1 1 1 1 1 1 1 1 -0.5 fe 1 1 1 1 1 1 1 0 -1.0 fd 1 1 1 1 1 1 0 1 -1.5 fc 1 1 1 1 1 1 0 0 -2.0 fb 1 1 1 1 1 0 1 1 -2.5 fa 1 1 1 1 1 0 1 0 -3.0 f9 1 1 1 1 1 0 0 1 -3.5 f8 1 1 1 1 1 0 0 0 -4.0 f7 1 1 1 1 0 1 1 1 -4.5 f6 1 1 1 1 0 1 1 0 -5.0 f5 1 1 1 1 0 1 0 1 -5.5 f4 1 1 1 1 0 1 0 0 -6.0 f3 1 1 1 1 0 0 1 1 -6.5 f2 1 1 1 1 0 0 1 0 -7.0 f1 1 1 1 1 0 0 0 1 -7.5 f0 1 1 1 1 0 0 0 0 -8.0 ef 1 1 1 0 1 1 1 1 -8.5 ee 1 1 1 0 1 1 1 0 -9.0 ed 1 1 1 0 1 1 0 1 -9.5 ec 1 1 1 0 1 1 0 0 -10.0 eb 1 1 1 0 1 0 1 1 -10.5 ea 1 1 1 0 1 0 1 0 -11.0 e9 1 1 1 0 1 0 0 1 -11.5 e8 1 1 1 0 1 0 0 0 -12.0 e7 1 1 1 0 0 1 1 1 -12.5 e6 1 1 1 0 0 1 1 0 -13.0 e5 1 1 1 0 0 1 0 1 -13.5 e4 1 1 1 0 0 1 0 0 -14.0 e3 1 1 1 0 0 0 1 1 -14.5 e2 1 1 1 0 0 0 1 0 -15.0 e1 1 1 1 0 0 0 0 1 -15.5 e0 1 1 1 0 0 0 0 0 -16.0 df 1 1 0 1 1 1 1 1 -16.5 de 1 1 0 1 1 1 1 0 -17.0 dd 1 1 0 1 1 1 0 1 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? -99.5 38 0 0 1 1 1 0 0 0 -100.0 37 0 0 1 1 0 1 1 1 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? mute 00 0 0 0 0 0 0 0 0
NJW1184 - 10 - b) auxiliary setting bit select address d7 d6 d5 d4 d3 d2 d1 d0 04h don?t care don?t care don?t care don?t care don?t care don?t care aux1 aux0 ? aux1/aux0: auxiliary port high/low ?0? : logic output ?low? ?1? : logic output ?high?
NJW1184 -11- ! typical characteristics supply current vs temparature v+=9v , vin=no signal , volume=0db 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 temparature [ ] supply current [ma] reference voltage vs tem parature v+=9v , vin=no signal , volume=0db 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 temparature [ ] reference voltage [v] supply current vs supply voltage vin=no signal , volume=0db 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 supply voltage [v] supply current [ma] ta=85 -40 25 reference voltage vs supply voltage vin=no signal , volume=0db 0 2 4 6 8 10 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 supply voltage[v] reference voltage[v] ta=85,25,-40 out noise vs tem parature v+=9v, rg=600 ? , a-weighting -120 -100 -80 -60 -40 -20 0 -50 -25 0 25 50 75 100 125 temparature [ ] out noise [dbv] vol=0db vol=mute mute level vs tem parature v+=9v, rg=600 ? ,vin=1vrms , a-weighting -120 -100 -80 -60 -40 -20 0 -50 -25 0 25 50 75 100 125 temparature [ ] mute level [db]
NJW1184 - 12 - ! typical characteristics thd+n vs input voltage (temparature) v+=9v, vin=ch1, f=1khz, volume=0db rg=600 ? , bw=400hz-30khz, vout=out1 0.01 0.1 1 10 0.01 0.1 1 10 input voltage [v] thd+n[% ] ta=85 25 -40 thd+n vs input voltage (volume control) v+=9v, vin=ch1, f=1khz, ta=25 rg=600 ? , bw=400hz-30khz, vout=out1 0.01 0.1 1 10 0.01 0.1 1 10 input voltage [v] thd+n [% ] vol=0db -10db -20db -30db channel separation vs frequency v+=9v , vin=1vrms , a-weighting , rg=600 ? vin:in2+in3+in4 , vout:out1 -100 -80 -60 -40 -20 0 10 100 1000 10000 100000 frequency [hz] channel separation[db] ta=85, 25, -40 channel separation vs frequency v+=9v , vin=1vrms , a-weighting , ta=25 rg=600 ? -100 -80 -60 -40 -20 0 10 100 1000 10000 100000 frequency [hz] channel separation [db] out1,out2,out3,out4 thd+n vs output voltage (temparature) v+=9v, vin=ch1, f=1khz, volume=0db rg=600 ? , bw=400hz-30khz, vout=out1 0.01 0.1 1 10 0.01 0.1 1 10 output voltage [v] thd+n [% ] ta=85 -40 25 thd+n vs output voltage (volume contorol) v+=9v, vin=ch1, f=1khz, ta=25 rg=600 ? , bw=400hz-30khz, vout=out1 0.01 0.1 1 10 0.01 0.1 1 10 output voltage [v] thd+n [% ] vol=0db -10db -20db -30db
NJW1184 -13- ! typical characteristics gain vs volum e control (tem parature ) v+=9v, rg=600 ? , vin=1vrms,vin=in1 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 20406080100120 volume control[db] gain[db] ta=85, 25, -40 vout=out1 channel balance vs volum e control (ch1-ch2) vin=1vrms,v+=9v -5 -4 -3 -2 -1 0 1 2 3 4 5 0 20406080100120 volume control [db] channel balance [db] ta=85, 25, -40 channel balance vs volum e control (ch3-ch4) vin=1vrms,v+=9v -5 -4 -3 -2 -1 0 1 2 3 4 5 0 20406080100120 volume control [db] channel balance [db] ta=-40 ta=85, 25 gain vs volum e control v+=9v, rg=600 ? , vin=1vrms,ta=25 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 20 40 60 80 100 120 volume control[db] gain[db] vout=out1,2,3,4 maxim um output voltage vs rl v+=9v, thd=1% 0 0.5 1 1.5 2 2.5 3 0.1 1 10 100 r l [k ? ] maximum output voltage [vrms ]
NJW1184 - 14 - [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

▲Up To Search▲

Price & Availability of NJW1184

	To Download NJW1184 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .